1. Technical Field
The present invention generally relates to semiconductor devices and, in particular, to a SiGe vertical gate contact for a gate conductor (GC) Post Etch Treatment (PET).
2. Background Description
In a vertical array device DRAM process a GC etch can remove excess vertical gate material to avoid shorts between word and bitlines. A PET acting to remove GC poly is problematic because the support devices/structures (hereinafter interchangeably referred to as xe2x80x9csupport structuresxe2x80x9d and xe2x80x9csupport devicesxe2x80x9d) are also exposed and, thus, would be negatively affected. As is known, the support structures are devices and/or structures that support the memory portion (e.g., transistors) of a semiconductor memory device.
FIGS. 1A and 1B are diagrams of a vertical gate that illustrate the problem with residues in the xe2x80x9ctraditionalxe2x80x9d vertical gate process with trench top spacer. Note that in FIGS. 1A and 1B, the vertical gate (108 and 109) is formed of vertical gate pedestal 109 and vertical gate area 108. The GC etch would be required to etch excess pedestal material out of a box 101 that is formed by the GC edge 102, the trench top nitride spacer 103 and the two sides 104, 105 bordering on isolation trench (IT) 106. The GC etch may leave poly-Si residues on the sidewalls of this box 101 that can later cause shorts to the bitline contact 107. That is, the bitline contact 107 is likely to short to the vertical gate (108 and 109); even more critical are the sides of the vertical gate pedestal 109 bordering on isolation trench (IT) 106 because these sidewalls are more vertical or even re-entrant.
Therefore, a need exists for a method of removing vertical gate residues in a vertical array without negatively affecting the support devices.
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a SiGe vertical gate contact for GC PET. The SiGe vertical gate contact allows for a PET step selective to support GC poly. Thus, the SiGe vertical gate contact advantageously removes vertical gate residues in a vertical array without negatively affecting the support devices.
According to an aspect of the present invention, there is provided a method for forming a vertical gate on a vertical array semiconductor device having support devices. The method comprises forming a deep trench top nitride spacer, forming a pedestal of the vertical gate from SiGe, and etching the pedestal in a gate conductor post etch treatment that is selective with respect to the support devices. The method further comprises forming a gate conductor SiN spacer, wherein the gate conductor SiN spacer and the deep trench top SiN spacer isolate a bitline contact from the vertical gate with respect to critical dimension and overlay.
According to another aspect of the present invention, the support devices are formed of poly Si.
According to yet another aspect of the present invention, there is provided a method for forming a vertical gate on a vertical array semiconductor device having support devices. The method comprises the step of forming the vertical gate from SiGe. The vertical gate is etched in a GC PET that is selective with respect to the support devices. An SiN GC spacer is folded back in a recess created by the GC PET to isolate a bitline contact from the vertical gate with respect to critical dimension and overlay.
According to still yet another aspect of the present invention, the support devices are formed of poly Si.
According to a further aspect of the present invention, the step of forming the vertical gate from SiGe eliminates any DT top spacer processing with respect to the vertical gate.